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rev. 1.1 flash memory cmos 8m (1m 8/512k 16) bit CSR2930800BA -90 n description the CSR2930800BA are a 8m-bit, 3.0 v-only flash memory organized as 1m bytes of 8 bits each or 512k words of 16 bits each. theCSR2930800BA are offered in a 48-pin tsop(i), 44-pin sop, and 48-ball fbga packages. these devices are designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. the standard CSR2930800BA offer access times 90 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the CSR2930800BA are pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the CSR2930800BA are programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the devices automatically time the erase pulse widths and verify proper cell margin. (continued) n product line up (continued) part no. CSR2930800BA ordering part no. v cc = 3.0 v +0.6 v C0.3 v -90 max address access time (ns) 90 max ce access time (ns) 90 max oe access time (ns) 35
CSR2930800BA -90 2 a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the devices also feature a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the CSR2930800BA are erased when shipped from the factory. the devices feature single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. the CSR2930800BA memories electrically erase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection. n packages 48-pin plastic tsop (i) 48-pin plastic fbga 48-pin plastic scsp (fpt-48p-m19) (bga-48p-m12) (wlp-48p-m03) marking side (wlp-48p-m03)
CSR2930800BA -90 3 n features ? single 3.0 v read, program, and erase minimizes system level power requirements ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 48-pin tsop(i) (package suffix: pftn C normal bend type) 48-ball fbga (package suffix: pbt) 48-ball scsp (package suffix: pw) ? minimum 100,000 program/erase cycles ? high performance 90 ns maximum access time ? sector erase architecture one 8k word, two 4k words, one 16k word, and fifteen 32k words sectors in word mode one 16k byte, two 8k bytes, one 32k byte, and fifteen 64k bytes sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase ? boot code sector architecture b = bottom sector ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode ? low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device ? sector protection hardware method disables any combination of sectors from program or erase operations ? sector protection set function by extended sector protect command ? temporary sector unprotection temporary sector unprotection via the reset pin *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
CSR2930800BA -90 4 n pin assignments (continued) a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 n.c. n.c. we reset n.c. n.c. ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CSR2930800BA normal bend tsop(i) a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 (marking side) (fpt-48p-m19)
CSR2930800BA -90 5 (continued) a1 a 3 a2 a 7 a3 ry/by a4 we a5 a 9 a6 a 13 b1 a 4 b2 a 17 b3 n.c. b4 reset b5 a 8 b6 a 12 c1 a 2 c2 a 6 c3 a 18 c4 n.c. c5 a 10 c6 a 14 d1 a 1 d2 a 5 d3 n.c. d4 n.c. d5 a 11 d6 a 15 e1 a 0 e2 dq 0 e3 dq 2 e4 dq 5 e5 dq 7 e6 a 16 f1 ce f2 dq 8 f3 dq 10 f4 dq 12 f5 dq 14 f6 byte g1 oe g2 dq 9 g3 dq 11 g4 v cc g5 dq 13 g6 dq 15 /a -1 h1 v ss h2 dq 1 h3 dq 3 h4 dq 4 h5 dq 6 h6 v ss scsp (top view) marking side (wlp-48p-m02) a6 b6 c6 d6 e6 f6 g6 h6 a5 b5 c5 d5 e5 f5 g5 h5 a4 b4 c4 d4 e4 f4 g4 h4 a3 b3 c3 d3 e3 f3 g3 h3 a2 b2 c2 d2 e2 f2 g2 h2 a1 b1 c1 d1 e1 f1 g1 h1 a 7 a 17 a 6 a 5 dq 0 dq 8 dq 9 dq 1 we reset n.c n.c dq 5 dq 12 dq 4 n.c dq 2 dq 10 dq 3 n.c ry/by a 9 a 8 a 10 a 11 dq 7 dq 14 dq 13 dq 6 dq 15 /a -1 byte a 13 a 12 a 14 a 15 a 16 v ss a 4 a 2 a 0 a 1 v ss a 3 ce oe dq 11 v cc a 18 a3 a1 a2 a6 a5 b1 b2 b3 b4 b5 b6 c1 c2 c3 c4 c5 c6 d1 d2 d3 d4 d5 d6 e1 e2 e3 e4 e5 e6 f1 f2 f3 f4 f5 f6 g1 g2 g3 g4 g5 g6 h1 h2 h3 h4 h5 h6 (top view) marking side bga-48p-m02 fbga a4
CSR2930800BA -90 6 n pin description pin name function a -1 , a 0 to a 18 address inputs dq 0 to dq 15 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector unprotection byte selects 8-bit or 16-bit mode v ss device ground v cc device power supply n.c. no internal connection
CSR2930800BA -90 7 n block diagram n logic symbol v ss v cc we ce a 0 to a 18 oe erase voltage generator dq 0 to dq 15 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb timer for program/erase a -1 byte reset ry/by buffer ry/by 19 a 0 to a 18 we oe ce dq 0 to dq 15 16 or 8 byte reset a -1 ry/by
CSR2930800BA -90 8 n device bus operation CSR2930800BA user bus operations table (byte = v ih ) legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see n dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see CSR2930800BA standard command definitions table. *2: refer to 7. sector protection in n functional descriptions. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 3.3 v 10% *5: it is also used for the extended sector protection. CSR2930800BA user bus operations table (byte = v il ) legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see n dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see CSR2930800BA standard command definitions table. *2: refer to 7. sector protection in n functional descriptions. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 3.3 v 10% *5: it is also used for the extended sector protection. operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 reset auto-select manufacturer code * 1 llhlllv id code h auto-select device code * 1 llhhllv id code h read * 3 llha 0 a 1 a 6 a 9 d out h standby hxxxxxx high-z h output disable l h h x x x x high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 d in h enable sector protection * 2, * 4 lv id lhlv id xh verify sector protection * 2, * 4 llhlhlv id code h temporary sector unprotection xxxxxxx x v id reset (hardware)/standby x x xxxxx high-z l operation ce oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 0 to dq 7 reset auto-select manufacturer code * 1 llhllllv id code h auto-select device code * 1 llhlhllv id code h read * 3 llha -1 a 0 a 1 a 6 a 9 d out h standby hxxxxxxxhigh-z h output disable lhhxxxxxhigh-z h write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in h enable sector protection * 2, * 4 lv id llhlv id xh verify sector protection * 2, * 4 llhllhlv id code h temporary sector unprotection * 5 xxxxxxxx x v id reset (hardware)/standby x x x x xxxxhigh-z l
CSR2930800BA -90 9 CSR2930800BA sector protection verify autoselect codes table *1: a -1 is for byte mode. *2: outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. expanded autoselect code table (b): byte mode (w): word mode hi-z: high-z type a 12 to a 18 a 6 a 1 a 0 a -1 *1 code (hex) manufactures code x v il v il v il v il 04h device code CSR2930800BA byte xv il v il v ih v il 5bh word x 225bh sector protection sector addresses v il v ih v il v il 01h *2 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0 000000000000100 device code CSR2930800BA (b) 5bh a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01011011 (w) 225bh 0010001001011011 sector protection 01h a -1 /0 000000000000001
CSR2930800BA -90 10 CSR2930800BA standard command definitions table notes: address bits a 11 to a 18 = x = h or l for all address commands except or program address (pa) and sector address (sa) bus operations are defined in CSR2930800BA user bus operations tables (byte = v ih and byte = v il ) . ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of we . the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 0 to a 10 byte mode: aaah or 555h to addresses a C1 and a 0 to a 10 both read/reset commands are functionally equivalent, resetting the device to the read mode. command combinations not described in CSR2930800BA standard command definitions table and CSR2930800BA extended command definitions table are illegal. command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset word 1xxxhf0h byte read/reset word 3 555h aah 2aah 55h 555h f0h ra rd byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h 555h 90h byte aaah 555h aaah program word 4 555h aah 2aah 55h 555h a0h pa pd byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h sector erase suspend erase can be suspended during sector erase with addr. (h or l). data (b0h) sector erase resume erase can be resumed after suspend with addr. (h or l). data (30h)
CSR2930800BA -90 11 CSR2930800BA extended command definitions table spa : sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd : sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1: this command is valid while fast mode. *2: this command is valid while reset =v id . *3: this data 00h is also acceptable . command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read cycle addr data addr data addr data addr data set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program* 1 word 2 xxxh a0hpapd byte xxxh reset from fast mode * 1 word 2 xxxh 90h xxxh f0h* 3 byte xxxh xxxh extended sector protect* 2 word 4 xxxh 60h spa 60h spa 40h spa sd byte
CSR2930800BA -90 12 n flexible sector-erase architecture ? one 16k byte, two 8k bytes, one 32k byte, and fifteen 64k bytes ? individual-sector, multiple-sector, or bulk-erase capability ? individual or multiple-sector protection is user definable. 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 32k byte 8k byte 8k byte 16k byte fffffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 07fffh 05fffh 03fffh 00000h 7ffffh 77fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 07fffh 03fffh 02fffh 01fffh 00000h CSR2930800BA sector architecture ( 16) ( 8)
CSR2930800BA -90 13 sector address table (CSR2930800BA) sector address a 18 a 17 a 16 a 15 a 14 a 13 a 12 address range ( 8) address range ( 16) sa0 0 0 0 0 0 0 x 00000h to 03fffh 00000h to 01fffh sa1 0 0 0 0 0 1 0 04000h to 05fffh 02000h to 02fffh sa2 0 0 0 0 0 1 1 06000h to 07fffh 03000h to 03fffh sa3 0 0 0 0 1 x x 08000h to 0ffffh 04000h to 07fffh sa4 0 0 0 1 x x x 10000h to 1ffffh 08000h to 0ffffh sa5 0 0 1 0 x x x 20000h to 2ffffh 10000h to 17fffh sa6 0 0 1 1 x x x 30000h to 3ffffh 18000h to 1ffffh sa7 0 1 0 0 x x x 40000h to 4ffffh 20000h to 27fffh sa8 0 1 0 1 x x x 50000h to 5ffffh 28000h to 2ffffh sa9 0 1 1 0 x x x 60000h to 6ffffh 30000h to 37fffh sa10 0 1 1 1 x x x 70000h to 7ffffh 38000h to 3ffffh sa11 1 0 0 0 x x x 80000h to 8ffffh 40000h to 47fffh sa12 1 0 0 1 x x x 90000h to 9ffffh 48000h to 4ffffh sa13 1 0 1 0 x x x a0000h to affffh 50000h to 57fffh sa14 1 0 1 1 x x x b0000h to bffffh 58000h to 5ffffh sa15 1 1 0 0 x x x c0000h to cffffh 60000h to 67fffh sa16 1 1 0 1 x x x d0000h to dffffh 68000h to 6ffffh sa17 1 1 1 0 x x x e0000h to effffh 70000h to 77fffh sa18 1 1 1 1 x x x f0000h to fffffh 78000h to 7ffffh
CSR2930800BA -90 14 n functional description 1. read mode the CSR2930800BA have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, it is necessary to input hardware reset or change ce pin from h or l 2. standby mode there are two ways to implement the standby mode on the CSR2930800BA devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a. the device can be read with standard access time (t ce ) from either of these standby modes. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current is consumed is less than 5 m a. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. 3. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of CSR2930800BA data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to activate this mode, CSR2930800BA automatically switch themselves to low power mode when CSR2930800BA addresses remain stably during access fine of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level). since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically and CSR2930800BA read-out the data for changed addresses. 4. output disable with the oe input at a logic high level (v ih ), output from the devices are disabled. this will cause the output pins to be in a high impedance state. 5. autoselect the autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , a 6 , and a -1 . (see CSR2930800BA sector protection verify autoselect codes table in n device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the CSR2930800BA are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in CSR2930800BA standard command definitions table ( n device bus operation). (refer to 2. autoselect command in n command definitions.)
CSR2930800BA -90 15 byte 0 (a 0 = v il ) represents the manufacturers code (04h) and (a 0 = v ih ) represents the device identifier code (CSR2930800BA = 5bh for 8 mode; CSR2930800BA = 225bh for 16 mode). these two bytes/words are given in "CSR2930800BA sector protection verify autoselect codes table" and "expanded autoselect code table" ( n device bus operation). all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see CSR2930800BA user bus operations tables (byte = v ih and byte = v il ) in n device bus operation.) 6. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. 7. sector protection the CSR2930800BA feature hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 18). the sector protection feature is enabled using programming equipment at the users site. the devices are shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il , and a 6 = v il . the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. "CSR2930800BA standard command definitions table" and "CSR2930800BA extended command definitions table" in n device bus operation define the sector address for each of the nineteen (19) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see 13. ac waveforms for sector protection timing diagram in n switching waveforms and 5. sector protection algorithm in n flow chart for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the devices will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to apply to v il on byte mode. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector address will produce a logical 1 at dq 0 for a protected sector. see "CSR2930800BA sector protection verify autoselect codes table" and "expanded autoselect code table" in n device bus operation for autoselect codes.
CSR2930800BA -90 16 8. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the CSR2930800BA devices in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again. see 14. temporary sector unprotection timing diagram in n switching waveforms and 6. temporary sector unprotection algorithm in n flow chart. 9. reset hardware reset the CSR2930800BA devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see 9. reset /ry/by timing diagram in n switching waveforms for the timing diagram. refer to 8. temporary sector unprotection for additional functionality. if hardware reset occurs during embedded erase algorithm, there is a possibility that the erasing sector(s) cannot be used.
CSR2930800BA -90 17 n command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. "CSR2930800BA standard command definitions table" in n device bus operation defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. 1. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the devices remain enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. 2. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the devices reside in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h for 16(xx02h for 8) returns the device code (CSR2930800BA = 5bh for 8 mode; CSR2930800BA = 225bh for 16 mode). (see "CSR2930800BA sector protection verify autoselect codes table" and "expanded autoselect code table" in n device bus operation.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address xx02h for 16 (xx04h for 8). scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be perform margin mode on the protected sector. (see CSR2930800BA user bus operations tables (byte = v ih and byte = v il ) in n device bus operation.) to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence.
CSR2930800BA -90 18 3. byte/word programming the devices are programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see hardware sequence flags table.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. 1. embedded program tm algorithm in n flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. 4. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see 8. write operation status.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) 2. embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. 5. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data=30h) is latched on the rising edge of we . after time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on "CSR2930800BA standard command definitions table" in n device bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 s otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs
CSR2930800BA -90 19 within the 50 m s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see 12. dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to 8. write operation status for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 18). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see 8. write operation status.) at which time the devices return to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase 2. embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. 6. erase suspend the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 20 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see 13. dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing.
CSR2930800BA -90 20 7. extended command (1) fast mode CSR2930800BA has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. (refer to 8. embedded program tm algorithm for fast mode in n flow chart extended algorithm.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to 8. embedded program tm algorithm for fast mode in n flow chart extended algorithm.) (3) extended sector protection in addition to normal sector protection, the CSR2930800BA has extended sector protection as extended func- tion. this function enable to protect sector by forcing v id on reset pin and write a commnad sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins), and write extended sector protect command (60h). a sector is typically protected in 150 m s. to verify programming of the protection circuitry, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector protect command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . 8. write operation status hardware sequence flags table *1: performing successive read operations from any address will cause dq 6 to toggle. *2: reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. notes: dq 0 and dq 1 are reserve pins for future use. dq 4 is internal use only. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle erase suspended mode erase suspend read (erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle * 1 00 1 * 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
CSR2930800BA -90 21 9. dq 7 data polling the CSR2930800BA devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in 3. data polling algorithm ( n flow chart). for chip erase and sector erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the CSR2930800BA data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see hardware sequence flags table.) see 6. ac waveforms for data polling during embedded algorithm operations in n switching waveforms for the data polling timing specifications and diagrams. 10. dq 6 toggle bit i the CSR2930800BA also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the devices will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see 7. ac waveforms for toggle bit i during embedded algorithm operations in n switching waveforms for the toggle bit i timing specifications and diagrams. 11. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma).
CSR2930800BA -90 22 the oe and we pins will control the output disable functions as described in CSR2930800BA user bus operations tables (byte = v ih and byte = v il ) in n device bus operation. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the devices were incorrectly used. if this occurs, reset the device with command sequence. 12. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags table. 13. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also hardware sequence flags table and 15. dq 2 vs. dq 6 in n switching waveforms. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. *1: performing successive read operations from any address will cause dq 6 to toggle. *2: reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle erase-suspend read (erase-suspended sector) * 1 1 1 toggle erase-suspend program dq 7 toggle * 1 1 * 2
CSR2930800BA -90 23 14. ry/by ready/busy the CSR2930800BA provide a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the devices are busy with either a program or erase operation. if the output is high, the devices are ready to accept any read/write or erase operation. when the ry/by pin is low, the devices will not accept any additional program or erase commands. if the CSR2930800BA are placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to 8. ry/by timing diagram during program/erase operations and 9. reset /ry/by timing diagram in n switching waveforms for a detailed timing diagram. the ry/ by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . 15. byte/word configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the CSR2930800BA devices. when this pin is driven high, the devices operate in the word (16-bit) mode. the data is read and programmed at dq 0 to dq 15 . when this pin is driven low, the devices operate in byte (8-bit) mode. under this mode, the dq 15 /a -1 pin becomes the lowest address bit and dq 8 to dq 14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 0 to dq 7 and the dq 8 to dq 15 bits are ignored. refer to 10. timing diagram for word mode configuration and 11. timing diagram for byte mode configuration and 12. byte timing diagram for write operations in n switching waveforms for the timing diagram. 16. data protection the CSR2930800BA are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automatically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. 17. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. 18. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. 19. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. 20. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
CSR2930800BA -90 24 n absolute maximum ratings *1: minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may undershoot v ss to C 2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc +0.5 v. during voltage transitions, outputs may overshoot to v cc +2.0 v for periods of up to 20 ns. *2: minimum dc input voltage on a 9 , oe and reset pins is C0.5 v. during voltage transitions, a9, oe and reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 , oe and reset pins is +13.0 v which may overshoot to 14.0 v for periods of up to 20 ns. voltage difference between input voltage and supply voltage (v in C v cc ) do not exceed 9 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating ranges note: operating ranges define those limits between which the functionality of the devices are guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their our representatives beforehand. parameter symbol rating unit min max storage temperature C55 +125 c ambient temperature with power applied C40 +85 c voltage with respect to ground all pins except a 9 , oe , reset * 1 C0.5 v cc +0.5 v v cc * 1 C0.5 +5.5 v a 9 , oe , and reset * 2 C0.5 +13.0 v parameter symbol conditions value unit min max ambient temperature t a ? C40 +85 c supply voltages v cc CSR2930800BA-90 +2.7 +3.6 v
CSR2930800BA -90 25 n maximum overshoot /maximum undershoot +0.6 v ?.5 v 20 ns ?.0 v 20 ns 20 ns figure 1 maximum undershoot waveform v cc +0.5 v +2.0 v v cc +2.0 v 20 ns 20 ns 20 ns figure 2 maximum overshoot waveform 1 +13.0 v v cc +0.5 v +14.0 v 20 ns 20 ns 20 ns *: this waveform is applied for a 9 , oe, and reset. figure 3 maximum overshoot waveform 2
CSR2930800BA -90 26 n dc characteristics *1: the i cc current listed includes both the dc operating current and the frequency dependent component (at 10 mhz). *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4: (v id C v cc ) do not exceed 9 v. parameter symbol test conditions value unit min max input leakage current i li v in = v ss to v cc , v cc = v cc max C1.0 +1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max C1.0 +1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max a 9 , oe , reset = 12.5 v 35 m a v cc active current * 1 i cc1 ce = v il , oe = v ih , f=10 mhz byte 22 ma word 25 ce = v il , oe = v ih , f=5 mhz byte 12 ma word 15 v cc active current * 2 i cc2 ce = v il , oe = v ih 35ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v 5 m a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v ss 0.3 v 5 m a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v 5a input low level v il C0.50.6v input high level v ih 2.0v cc +0.3 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4 v id 11.5 12.5 v output low voltage level v ol i ol = 4.0 ma, v cc = v cc min 0.45 v output high voltage level v oh1 i oh = C2.0 ma, v cc = v cc min 2.4 v v oh2 i oh = C100 m av cc C0.4 v low v cc lock-out voltage v lko 2.32.5v
CSR2930800BA -90 27 n ac characteristics ? read only operations characteristics note: test conditions: output load: 1 ttl gate and 100 pf (CSR2930800BA-90) input rise and fall times: 5 ns input pulse levels: 0.0 v or 3.0 v timing measurement reference level input: 1.5 v output:1.5 v parameter symbol test setup value * unit -90 jedec standard min max read cycle time t avav t rc 90ns address to output delay t avqv t acc ce = v il oe = v il 90ns chip enable to output delay t elqv t ce oe = v il 90ns output enable to output delay t glqv t oe 35ns chip enable to output high-z t ehqz t df 30ns output enable to output high-z t ghqz t df 30ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh 0ns reset pin low to read mode t ready 20 m s ce to byte switching low or high t elfl t elfh 5ns c l v cc diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w figure 4 test conditions notes : c l = 100 pf including jig capacitance (CSR2930800BA-90)
CSR2930800BA -90 28 ? write/erase/program operations *1: this does not include the preprogramming time. *2: this timing is for sector protection operation. parameter symbol -90 unit jedec standard min typ max write cycle time t avav t wc 90 ?? ns address setup time t avwl t as 0 ?? ns address hold time t wlax t ah 45 ?? ns data setup time t dvwh t ds 45 ?? ns data hold time t whdx t dh 0 ?? ns output enable setup time t oes 0 ?? ns output enable hold time read t oeh 0 ?? ns toggle and data polling 10 ?? ns read recover time before write t ghwl t ghwl 0 ?? ns read recover time before write t ghel t ghel 0 ?? ns ce setup time t elwl t cs 0 ?? ns we setup time t wlel t ws 0 ?? ns ce hold time t wheh t ch 0 ?? ns we hold time t ehwh t wh 0 ?? ns write pulse width t wlwh t wp 45 ?? ns ce pulse width t eleh t cp 45 ?? ns write pulse width high t whwl t wph 25 ?? ns ce pulse width high t ehel t cph 25 ?? ns byte programming operation t whwh1 t whwh1 ? 8 ? s sector erase operation * 1 t whwh2 t whwh2 ? 1 ? sec v cc setup time t vcs 50 ?? s rise time to v id * 2 t vidr 500 ?? ns voltage transition time * 2 t vlht 4 ?? s write pulse width * 2 t wpp 100 ?? s oe setup time to we active * 2 t oesp 4 ?? s ce setup time to we active * 2 t csp 4 ?? s recover time from ry/by t rb 0 ?? ns reset pulse width t rp 500 ?? ns reset hold time before read t rh 200 ?? ns byte switching low to output high-z t flqz ?? 35 ns byte switching high to output active t fhqv 35 ?? ns program/erase valid to ry/by delay t busy ?? 90 ns delay time from embedded output enable t eoe ?? 35 ns
CSR2930800BA -90 29 n erase and programming performance n pin capacitance tsop(i) notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipula by output capacitance. fbga notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipula by output capacitance. scsp notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipula by output capacitance. parameter limit unit comments min typ max sector erase time 1 10 s excludes programming time prior to erasure word programming time 16 360 m s excludes system-level overhead byte programming time 8 300 m s chip programming time 8.4 25 s excludes system-level overhead program/erase cycle 100,000 cycle parameter symbol test setup typ max unit input capacitance c in v in = 0 7.5 9.5 pf output capacitance c out v out = 0 8.0 10.0 pf control pin capacitance c in2 v in = 0 10.0 13.0 pf parameter symbol test setup typ max unit input capacitance c in v in = 0 7.5 9.5 pf output capacitance c out v out = 0 8.0 10.0 pf control pin capacitance c in2 v in = 0 10.0 13.0 pf parameter symbol test setup typ max unit input capacitance c in v in = 0 7.5 9.5 pf output capacitance c out v out = 0 8.0 10.0 pf control pin capacitance c in2 v in = 0 10.0 13.0 pf
CSR2930800BA -90 30 n switching waveforms ? key to switching waveforms 1. ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h ??or ? any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance ?ff?state we oe ce t acc t df t ce t oe outputs t rc address address stable high-z output valid high-z t oeh
CSR2930800BA -90 31 2. ac waveforms for hardware reset/read operations 3. ac waveforms for alternate we controlled program operations reset t acc t oh outputs t rc address address stable high-z output valid t rh t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out notes: pa is address of the memory location to be programmed. pd is data to be programmed at byte address. d q 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
CSR2930800BA -90 32 4. ac waveforms for alternate ce controlled program operations t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd notes: pa is address of the memory location to be programmed. pd is data to be programmed at byte address. d q 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
CSR2930800BA -90 33 5. ac waveforms chip/sector erase operations v cc ce oe address data t wp we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h/ 30h 10h for chip erase * sa is the sector address for sector erase. addresses = 555h (word), aaah (byte) for chip erase. note: these waveforms are for the 16 mode. the addresses differ from 8 mode. :
CSR2930800BA -90 34 6. ac waveforms for data polling during embedded algorithm operations 7. ac waveforms for toggle bit i during embedded algorithm operations t oeh t oe t whwh1 or 2 ce oe t eoe we data t df t ch t ce high-z high-z dq 7 = valid data dq 0 to dq 6 valid data dq 7 * dq 7 dq 0 to dq 6 data dq 0 to dq 6 = output flag *: dq 7 = valid data (the device has completed the embedded operation). t oeh ce we oe dq 6 data dq 6 = toggle dq 6 = toggle dq 6 = stop toggling valid * t oe t oes *: dq 6 stops toggling (the device has completed the embedded operation).
CSR2930800BA -90 35 8. ry/by timing diagram during program/erase operations 9. reset /ry/by timing diagram 10. timing diagram for word mode configuration rising edge of the last we signal ce ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb ce byte t elfh t fhqv a -1 data output (dq 0 to dq 7 ) dq 15 dq 15 /a -1 dq 0 to dq 14 (dq 0 to dq 14 ) data output
CSR2930800BA -90 36 11. timing diagram for byte mode configuration 12. byte timing diagram for write operations ce byte dq 15 /a -1 dq 0 to dq 14 t elfl dq 15 a -1 t flqz data output (dq 0 to dq 7 ) (dq 0 to dq 14 ) data output falling edge of the last write signal t hold ce or we (t ah ) t set (t as ) input valid byte
CSR2930800BA -90 37 13. ac waveforms for sector protection timing diagram t vlht sax a 18 , a 17 , a 16 a 15 , a 14 a 13 , a 12 say a 0 a 6 a 9 12 v 3 v t vlht oe 12 v 3 v t vlht t vlht t oesp t wpp t csp we ce t oe 01h data v cc a 1 t vcs sax : sector address for initial sector say : sector address for next sector note: a -1 is v il on byte mode.
CSR2930800BA -90 38 14. temporary sector unprotection timing diagram 15. dq 2 vs. dq 6 12 v 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr unprotection period t vlht dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce note dq 2 is read from the erase-suspended sector.
CSR2930800BA -90 39 16. extended sector protection timing diagram spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 150 m s (min) spay reset a 6 oe we ce data a 1 v cc a 0 add spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe
CSR2930800BA -90 40 n flow chart 1. embedded program tm algorithm no yes program command sequence* (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address last address ? program address/program data start programming completed embedded algorithms *: the sequence is applied for 16 mode. the addresses differ from 8 mode.
CSR2930800BA -90 41 2. embedded erase tm algorithm 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequece (see below) data polling or toggle bit successfully completed chip erase command sequence* (address/command): individual sector/multiple sector* erase command sequence (address/command): sector address/30h sector address/30h sector address/30h erasure completed start embedded algorithms *: the sequence is applied for 16 mode. the addresses differ from 8 mode.
CSR2930800BA -90 42 3. data polling algorithm dq 7 = data? no no dq 7 = data? dq 5 = 1? yes yes no read (dq 0 to dq 7 ) addr. = va read (dq 0 to dq 7 ) addr. = va yes start fail pass note: dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = byte address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = any of the sector addresses within the sector not being protected during chip erase
CSR2930800BA -90 43 4. toggle bit algorithm dq 6 = toggle ? yes no dq 6 = toggle ? dq 5 = 1? yes no no yes read (dq 0 to dq 7 ) addr. = va read (dq 0 to dq 7 ) addr. = "h" or "l" start pass fail note: dq 6 is rechecked even if dq 5 = 1 because dq 6 may stop toggling at the same time as dq 5 changing to 1.
CSR2930800BA -90 44 5. sector protection algorithm setup sector addr. (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id , a 6 = ce = v il , reset = v ih a 0 = v il , a 1 = v ih plscnt = 1 time out 100 m s read from sector (addr. = sa, a 0 = v il , a 1 = v ih , a 6 = v il )* remove v id from a 9 write reset command increment plscnt no yes protect another sector? data = 01h? plscnt = 25? device failed remove v id from a 9 write reset command start sector protection completed *: a -1 is v il on byte mode.
CSR2930800BA -90 45 6. temporary sector unprotection algorithm reset = v id (note 1) perform erase or program operations reset = v ih start temporary sector unprotection completed (note 2) notes: all protected sectors are unprotected. all previously protected sectors are protected once again.
CSR2930800BA -90 46 7. extended sector protection algorithm to sector protection yes no no plscnt = 1 no yes protection other sector start sector protection extended sector plscnt = 25? device failed remove v id from reset completed remove v id from reset write reset command write reset command reset = v id wait to 4 m s protection entry? to setup sector protection write xxxh/60h write spa/60h (a 0 = v il , a 1 = v ih , a 6 = v il ) time out 150 m s to verify sector protection write spa/40h (a 0 = v il , a 1 = v ih , a 6 = v il ) data = 01h? ? device is operating in temporary sector read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) increment plscnt setup next sector address no yes yes unprotection mode fast mode algorithm
CSR2930800BA -90 47 8. embedded program tm algorithm for fast mode fast mode algorithm start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify byte? no program address/program data data polling device last address ? programming completed xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode *: the sequence is applied for 16 mode. the addresses differ from 8 mode.
CSR2930800BA -90 48 n ordering information standard products standard products are available in several packages. the order number is formed by a combination of: csr2930800 b a -90 pftn device number/description csr2930800 8mega-bit (1m 8-bit or 512k 16-bit) cmos flash memory 3.0 v-only read, program, and erase package type pftn = 48-pin thin small outline package (tsop) normal bend pbt-= 48-ball fine pitch ball grid array package (fbga:bga-48p-m12) pw-= 48-ball super chip size package (scsp) speed option see product selector guide device revision boot code sector architecture b = bottom sector
CSR2930800BA -90 49 n package dimensions 48-pin plastic tsop(1) (fpt-48p-m19) note 1: * resin protrusion. (each side: 0.15(.006)max) note 2: pins width and pins thickness include plating thickness. 48-pin plastic fbga (bga-48p-m12) C .003 +.001 C 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 * * lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 typ 0.50(.020) (.453) 11.50ref (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2001 fujitsu limited f48029s-c-4-5 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part dimensions in mm (inches) c 2001 fujitsu limited b48012s-c-3-3 9.000.20(.354.008) 0.380.10(.015.004) (stand off) (mounting height) 6.000.20 (.236.008) 0.10(.004) 0.80(.031)typ 5.60(.220) 4.00(.157) 48-?0.450.10 (48-?.018.004) m ?0.08(.003) index h g fed c ba 6 5 4 3 2 1 c0.25(.010) .041 C.004 +.006 C0.10 +0.15 1.05 dimensions in mm (inches)
CSR2930800BA -90 50 48-pin plastic scsp (wlp-48p-m03) c 2001 fujitsu limited w48003s-c-1-1 7.060.10(.278.004) 3.520.10 (.139.004) (laser marking) 0.10(.004) z (3.50=0.50x7) 0.50(.020) typ 0.50(.020) typ 48-?0.350.10 (48-?.014.004) m 0.08(.003) z 4-?0.13(4-?.005) x y index area 0.25(.010) min. (stand off) 1.00(.039) ((.138=.020x7)) (2.50=0.50x5) ((.098=.020x5)) xyz (2.25) ((.089)) (0.25(.010) (0.13sq) ((.005sq)) (index) max. dimensions in mm (inches)

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